18 search results - page 2 / 4 » Reduction of CMOS Power Consumption and Signal Integrity Iss... |
FPGA
2004
ACM
13 years 11 months ago
2004
ACM
We consider active leakage power dissipation in FPGAs and present a “no cost” approach for active leakage reduction. It is well-known that the leakage power consumed by a digi...
ISCAS
2007
IEEE
14 years 19 days ago
2007
IEEE
— Employing multiple supply voltages (multi-VDD) is attractive for reducing the power consumption without sacrificing the speed of an integrated circuit (IC). In order to transfe...
EMSOFT
2005
Springer
13 years 12 months ago
2005
Springer
Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies. Recent research efforts have tried to integrate architecture...
FPGA
2010
ACM
14 years 3 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
FPGA
2007
ACM
14 years 16 days ago
2007
ACM
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...