Coarse-grained reconfigurable architectures aim to achieve both goals of high performance and flexibility. However, existing reconfigurable array architectures require many resour...
Yoonjin Kim, Mary Kiemb, Chulsoo Park, Jinyong Jun...
This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a tec...
Francisco Barat, Murali Jayapala, Pieter Op de Bee...
This paper presents a new and retargetable method to identify patterns of instructions with direct support in coarsegrained processing elements (PEs). The method uses a three-addr...
Modern reconfigurable computing systems feature powerful hybrid architectures with multiple microprocessor cores, large reconfigurable logic arrays and distributed memory hierarch...
The architecture and use of caches for two-level reconfigurable hardware is studied in this paper. The considered two-level reconfigurable hardware performs ordinary reconfiguratio...