199 search results - page 13 / 40 » Register pointer architecture for efficient embedded process... |
124
Voted
IPPS
2007
IEEE
15 years 8 months ago
2007
IEEE
An innovative technique to model and simulate partial and dynamic reconfigurable processors is presented in this paper. The basis for development is a SystemC kernel modified for ...
111
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VLSID
2007
IEEE
16 years 2 months ago
2007
IEEE
We present a technique for automatic verification of pipelined microprocessors using model checking. Antecedent conditioned slicing is an efficient abstraction technique for hardw...
125
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CASES
2006
ACM
15 years 7 months ago
2006
ACM
The architectural design of embedded systems is becoming increasingly idiosyncratic to meet varying constraints regarding energy consumption, code size, and execution time. Tradit...
117
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RSP
2005
IEEE
15 years 7 months ago
2005
IEEE
Nowadays, Architecture Description Languages (ADLs) are getting popular to speed up the development of complex SoC design, by performing the design space explon a higher level of ...
166
Voted
HPCA
2006
IEEE
16 years 2 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...