199 search results - page 25 / 40 » Register pointer architecture for efficient embedded process... |
101
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IPPS
2007
IEEE
15 years 6 months ago
2007
IEEE
Hardware accelerators are increasingly used to extend the computational capabilities of baseline scalar processors to meet the growing performance and power requirements of embedd...
ISORC
2008
IEEE
15 years 6 months ago
2008
IEEE
Java, as a safe and platform independent language, avoids access to low-level I/O devices or direct memory access. In standard Java, low-level I/O it not a concern; it is handled ...
104
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DAC
2005
ACM
15 years 1 months ago
2005
ACM
This paper focuses on designing network processing software for embedded processors. Our design flow CRACC represents an efficient path to implementation based on a modular applic...
253
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Presentation
Data-parallel architectures like SIMD (Single Instruction Multiple Data) or SIMT (Single Instruction Multiple Thread) have been adopted in many recent CPU and GPU architectures. Al...
108
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DATE
2008
IEEE
2008
IEEE
State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores
15 years 1 months ago
1 We present a new type of Linear Feedback Shift Registers, State Skip LFSRs. State Skip LFSRs are normal LFSRs with the addition of a small linear circuit, the State Skip circuit,...