1179 search results - page 30 / 236 » Relative Timing Based Verification of Timed Circuits and Sys... |
107
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EMSOFT
2006
Springer
15 years 3 months ago
2006
Springer
Upper bounds on worst-case execution times, which are commonly called WCET, are a prerequisite for validating the temporal correctness of tasks in a real-time system. Due to the e...
101
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FORMATS
2008
Springer
15 years 1 months ago
2008
Springer
Verification of partially synchronous distributed systems is difficult because of inherent concurrency and the potentially large state space of the channels. This paper identifies ...
109
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MJ
2007
14 years 11 months ago
2007
With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes...
124
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DAC
1998
ACM
15 years 4 months ago
1998
ACM
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
AHS
2006
IEEE
15 years 5 months ago
2006
IEEE
The paper presents a novel integrated system in which a number of image processing algorithm are embedded within a Genetic Algorithm (GA) based framework in order to provide an ad...