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VLSID
2002
IEEE
130views VLSI» more  VLSID 2002»
16 years 7 days ago
Using Randomized Rounding to Satisfy Timing Constraints of Real-Time Preemptive Tasks
In preemptive real-time systems, a tighter estimate of the Worst Case Response Time(WCRT) of the tasks can be obtained if the layout of the tasks in memory is included in the esti...
Anupam Datta, Sidharth Choudhury, Anupam Basu
CODCRY
2009
Springer
111views Cryptology» more  CODCRY 2009»
15 years 6 months ago
On the Impossibility of Strong Encryption Over
We give two impossibility results regarding strong encryption over an infinite enumerable domain. The first one relates to statistically secure one-time encryption. The second on...
Raphael C.-W. Phan, Serge Vaudenay
ASYNC
2007
IEEE
131views Hardware» more  ASYNC 2007»
15 years 6 months ago
High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link
A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67Gbps throughpu...
Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia...
89
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ICMCS
2000
IEEE
102views Multimedia» more  ICMCS 2000»
15 years 4 months ago
Trader's Quality of Service Specifications and Effects on System Performance for Video-on-Demand
In this paper we present a detailed review on the Trader’s Quality of Service (QoS) Specifications and the Effects on System Performance for Video-on-Demand Multimedia (MM) Appl...
Edward Babulak
ISLPED
1996
ACM
72views Hardware» more  ISLPED 1996»
15 years 4 months ago
Simultaneous buffer and wire sizing for performance and power optimization
In this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay and power dissipation minimization. We prove the BS/WS relation for optimal SBWS solutions...
Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung