174 search results - page 14 / 35 » Reliability-Centric High-Level Synthesis |
FDL
2007
IEEE
15 years 3 months ago
2007
IEEE
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
IPPS
2007
IEEE
15 years 3 months ago
2007
IEEE
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
84
Voted
DATE
2002
IEEE
15 years 2 months ago
2002
IEEE
Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...
57
Voted
ASAP
2000
IEEE
15 years 1 months ago
2000
IEEE