74 search results - page 3 / 15 » Reordering Algorithm for Minimizing Test Power in VLSI Circu... |
VLSID
2002
IEEE
14 years 6 months ago
2002
IEEE
In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power ...
DAC
2004
ACM
13 years 10 months ago
2004
ACM
This paper presents a method of generating tests for transition faults using tests for stuck-at faults such that the peak power is the minimum possible using a given set of tests ...
VTS
2006
IEEE
14 years 7 days ago
2006
IEEE
— In this paper, an algorithm for scan vector ordering, PEAKASO, is proposed to minimize the peak temperature during scan testing. Given a circuit with scan and the scan vectors,...
ICCAD
1995
IEEE
13 years 9 months ago
1995
IEEE
Pad assignment with signal integrity optimization is very important for high-speed VLSI design. In this paper, an efficient method is proposed to effectively minimize both simulta...
EVOW
1999
Springer
13 years 10 months ago
1999
Springer
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...