34 search results - page 5 / 7 » Reusing Scan Chains for Test Pattern Decompression |
111
Voted
DAC
2007
ACM
16 years 3 months ago
2007
ACM
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
101
Voted
VTS
2005
IEEE
15 years 8 months ago
2005
IEEE
A new method for test resource partitioning is introduced which keeps the design-for-test logic independent of the test set and moves the test pattern dependent information to an ...
120
Voted
ASPDAC
2007
ACM
15 years 6 months ago
2007
ACM
As the large size of test data volume is becoming one of the major problems in testing System-on-a-Chip (SoC), several compression coding schemes have been proposed. Extended frequ...
130
Voted
DSD
2010
IEEE
15 years 2 months ago
2010
IEEE
—Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated i...
113
click to vote
DAC
1997
ACM
15 years 6 months ago
1997
ACM
This paper presents a new scan-based BIST scheme which achieves very high fault coverage without the deficiencies of previously proposed schemes. This approach utilizes scan order...