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HPCA
1996
IEEE
15 years 2 months ago
Co-Scheduling Hardware and Software Pipelines
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded process...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...
ICPP
1994
IEEE
15 years 2 months ago
An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors
Both hardware and software prefetching have been shown to be e ective in tolerating the large memory latencies inherent in shared-memory multiprocessors however, both types of pre...
Edward H. Gornish, Alexander V. Veidenbaum
CGI
2001
IEEE
15 years 1 months ago
Hardware-Accelerated Rendering of Antialiased Shadows with Shadow Maps
We present a hardware-accelerated method for rendering high quality, antialiased shadows using the shadow map approach. Instead of relying on dedicated hardware support for shadow...
Stefan Brabec, Hans-Peter Seidel
74
Voted
BILDMED
2008
129views Algorithms» more  BILDMED 2008»
14 years 11 months ago
Evaluating the Performance of Processing Medical Volume Data on Graphics Hardware
With the broad availability and increasing performance of commodity graphics processors (GPU), non-graphical applications have become an active field of research. However, leveragi...
Matthias Raspe, Guido Lorenz, Stefan Müller 0...
ERSA
2009
147views Hardware» more  ERSA 2009»
14 years 7 months ago
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
Kylan Robinson, José G. Delgado-Frias