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133
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ASPDAC
2005
ACM
15 years 6 months ago
2005
ACM
— We present SoCExplore, a framework for fast communicationcentric design space exploration of complex SoCs with networkbased interconnects. Speed-up in exploration is achieved t...
120
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ASPDAC
2005
ACM
15 years 6 months ago
2005
ACM
Abstract— This paper presents a post-route gate-sizing algorithm for coupling-noise reduction that constrains the yield loss under process variations. Algorithms for coupling-noi...
119
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ASAP
2010
IEEE
15 years 6 months ago
2010
IEEE
urrence abstractions Arpith C. Jacob Jeremy D. Buhler Roger D. Chamberlain Arpith C. Jacob, Jeremy D. Buhler, and Roger D. Chamberlain, "Design of ut-optimized arrays from rec...
145
Voted
PDPTA
2008
15 years 6 months ago
2008
- For an iterative process to be parallelized, the operations that comprise the process must be organized into a correct schedule that will allow the hardware to compute the task. ...
124
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SBACPAD
2004
IEEE
15 years 6 months ago
2004
IEEE
The aim of the paper is to introduce techniques in order to optimize the parallel execution time of sorting on heterogeneous platforms (processors speeds are related by a constant...