Yield driven gate sizing for coupling-noise reduction under uncertainty

Abstract— This paper presents a post-route gate-sizing algorithm for coupling-noise reduction that constrains the yield loss under process variations. Algorithms for coupling-noise reduction which do not consider uncertainty in the manufacturing process can make a circuit susceptible to failure. Using probabilistic models, the coupling-noise reduction problem is solved as a fixpoint computation problem on a lattice. A novel gate-sizing algorithm with low area overhead is proposed for coupling-noise reduction under uncertainty. Experimental results are reported for the ISCAS benchmarks and larger circuits with comparisons to traditional approaches.

• Type: Conference
• Year: 2005
• Where: ASPDAC
• Authors: Debjit Sinha, Hai Zhou
• Keywords: ASPDAC 2005, Coupling-noise Reduction, Coupling-noise Reduction Problem, Gate-sizing Algorithm, Hardware