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ACSD
2010
IEEE
215views Hardware» more  ACSD 2010»
15 years 3 months ago
A Formal Semantics of Clock Refinement in Imperative Synchronous Languages
The synchronous model of computation divides the execution of a program into an infinite sequence of socalled macro steps, which are further divided into finitely many micro steps....
Mike Gemunde, Jens Brandt, Klaus Schneider
ASPDAC
2010
ACM
143views Hardware» more  ASPDAC 2010»
15 years 3 months ago
Constrained global scheduling of streaming applications on MPSoCs
Abstract-- We present a global scheduling framework for synchronous data flow (SDF) streaming applications on MPSoCs, based on optimized computation and contention-free routing. Th...
Jun Zhu, Ingo Sander, Axel Jantsch
ASPDAC
2010
ACM
137views Hardware» more  ASPDAC 2010»
15 years 3 months ago
Improved on-chip router analytical power and area modeling
Over the course of this decade, uniprocessor chips have given way to multi-core chips which have become the primary building blocks of today's computer systems. The presence o...
Andrew B. Kahng, Bill Lin, Kambiz Samadi
ASPDAC
2010
ACM
135views Hardware» more  ASPDAC 2010»
15 years 3 months ago
Statistical timing verification for transparently latched circuits through structural graph traversal
Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will ada...
Xingliang Yuan, Jia Wang
MST
2011
208views Hardware» more  MST 2011»
15 years 1 days ago
Weighted Picture Automata and Weighted Logics
The theory of two-dimensional languages, generalizing formal string languages, was motivated by problems arising from image processing and models of parallel computing. Weighted au...
Ina Fichtner