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» Route Packets, Not Wires: On-Chip Interconnection Networks
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SLIP
2009
ACM
14 years 23 days ago
Integrated interlayer via planning and pin assignment for 3D ICs
As technology advances, 3D ICs are introduced for alleviating the interconnect problem coming with shrinking feature size and increasing integration density. In 3D ICs, one of the...
Xu He, Sheqin Dong, Xianlong Hong, Satoshi Goto
CODES
2008
IEEE
13 years 8 months ago
ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip
The performance of system-on-chip is determined not only by the performance of its functional units, but also by how efficiently they cooperate with one another. It is the on-chip...
Huaxi Gu, Jiang Xu, Zheng Wang
ICPP
2007
IEEE
14 years 17 days ago
Tightly-Coupled Multi-Layer Topologies for 3-D NoCs
Three-dimensional Network-on-Chip (3-D NoC) is an emerging research topic exploring the network architecture of 3-D ICs that stack several smaller wafers for reducing wire length ...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...
CORR
1998
Springer
110views Education» more  CORR 1998»
13 years 6 months ago
laboratories for Data Communications and Computer Networks
Abstract In this paper we describe a hands-on laboratory oriented instructional package that we have developed for data communications and networking. The package consists of a sof...
Rohit Goyal, Steve Lai, Raj Jain, Arjan Durresi
CN
2008
108views more  CN 2008»
13 years 4 months ago
An approach to the identification of network elements composing heterogeneous end-to-end paths
Today's networks are becoming increasingly complex and the ability to effectively and efficiently operate and manage them is ever more challenging. Ways to provide end-to-end...
Alessio Botta, Antonio Pescapè, Giorgio Ven...