149 search results - page 10 / 30 » Routing Lookups in Hardware at Memory Access Speeds |
190
click to vote
ISCA
2012
IEEE
13 years 2 months ago
2012
IEEE
Most modern cores perform a highly-associative translation look aside buffer (TLB) lookup on every memory access. These designs often hide the TLB lookup latency by overlapping it...
CCECE
2006
IEEE
15 years 5 months ago
2006
IEEE
— Edge detection is a computer vision algorithm that is very processor intensive. It is possible to increase the speed of the algorithm by using hardware parallelism. This paper ...
ISLPED
2006
ACM
15 years 5 months ago
2006
ACM
This paper presents an energy-conservation method for multiple disks and their cache memory. Our method periodically resizes the cache memory and controls the rotation speeds unde...
IPOM
2009
Springer
15 years 6 months ago
2009
Springer
Abstract. The IPv4 addressing scheme has been the standard for Internet communication since it was established in the 1960s. However, the enormous increase in Internet traffic usag...
104
click to vote
FPGA
1997
ACM
15 years 3 months ago
1997
ACM
This paper shows that the speed of FPGAs with large embedded memory arrays can be improved by adding direct programmable connections between the memories. Nets that connect to mul...