Sciweavers

261 search results - page 20 / 53
» SAT-Based Algorithms for Logic Minimization
Sort
View
ASPDAC
2007
ACM
80views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Recognition of Fanout-free Functions
Factoring is a logic minimization technique to represent a Boolean function in an equivalent function with minimum literals. When realizing the circuit, a function represented in ...
Tsung-Lin Lee, Chun-Yao Wang
DAC
1996
ACM
15 years 1 months ago
Test Point Insertion: Scan Paths through Combinational Logic
We propose a low-overhead scan design methodology which employs a new test point insertion technique to establish scan paths through the functional logic. The technique re-uses th...
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-T...
INFOCOM
2010
IEEE
14 years 8 months ago
Overcoming Failures: Fault-tolerance and Logical Centralization in Clean-Slate Network Management
—We investigate the design of a clean-slate control and nt plane for data networks using the abstraction of 4D architecture, utilizing and extending 4D’s concept of logically c...
Hammad Iqbal, Taieb Znati
ACL
1990
14 years 11 months ago
Automated Inversion of Logic Grammars for Generation
We describe a system of reversible grammar in which, given a logic-grammar specification of a natural language, two efficient PROLOGprograms are derived by an off-line compilation...
Tomek Strzalkowski, Ping Peng
EURODAC
1990
IEEE
102views VHDL» more  EURODAC 1990»
15 years 1 months ago
Tools and devices supporting the pseudo-exhaustive test
: In this paper logical cells and algorithms are presented supporting the design of pseudo-exhaustively testable circuits. The approach is based on real hardware segmentation, inst...
Sybille Hellebrand, Hans-Joachim Wunderlich