Sciweavers

261 search results - page 39 / 53
» SAT-Based Algorithms for Logic Minimization
Sort
View
DATE
2006
IEEE
140views Hardware» more  DATE 2006»
15 years 3 months ago
Optimization of regular expression pattern matching circuits on FPGA
Regular expressions are widely used in Network Intrusion Detection System (NIDS) to represent patterns of network attacks. Since traditional software-only NIDS cannot catch up to ...
Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang,...
DAC
1997
ACM
15 years 2 months ago
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha C...
JAIR
2008
123views more  JAIR 2008»
14 years 9 months ago
CTL Model Update for System Modifications
Model checking is a promising technology, which has been applied for verification of many hardware and software systems. In this paper, we introduce the concept of model update to...
Yan Zhang, Yulin Ding
INFOCOM
2007
IEEE
15 years 4 months ago
Distributed Low-Complexity Maximum-Throughput Scheduling for Wireless Backhaul Networks
— We introduce a low-complexity distributed slotted MAC protocol that can support all feasible arrival rates in a wireless backhaul network (WBN). For arbitrary wireless networks...
Abdul Kader Kabbani, Theodoros Salonidis, Edward W...
GECCO
2007
Springer
189views Optimization» more  GECCO 2007»
15 years 4 months ago
A more bio-plausible approach to the evolutionary inference of finite state machines
With resemblance of finite-state machines to some biological mechanisms in cells and numerous applications of finite automata in different fields, this paper uses analogies an...
Hooman Shayani, Peter J. Bentley