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VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
15 years 6 months ago
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures
With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of poweraware design methodologies have resulted in potentially significa...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
VLSID
2002
IEEE
149views VLSI» more  VLSID 2002»
16 years 20 hour ago
Functional Partitioning for Low Power Distributed Systems of Systems-on-a-Chip
In this paper, we present a functional partitioning method for low power real-time distributed embedded systems whose constituent nodes are systems-on-a-chip (SOCs). The systemlev...
Yunsi Fei, Niraj K. Jha
AHS
2006
IEEE
142views Hardware» more  AHS 2006»
15 years 5 months ago
On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition
To increase the flexibility of single-chip evolvable hardware systems, we explore possibilities of systems with the evolutionary algorithm implemented in software on an onchip pr...
Kyrre Glette, Jim Torresen, Moritoshi Yasunaga, Yo...
EMSOFT
2005
Springer
15 years 5 months ago
Optimizing inter-processor data locality on embedded chip multiprocessors
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...
Guilin Chen, Mahmut T. Kandemir
CHI
2009
ACM
16 years 7 days ago
A personalized walk through the museum: the CHIP interactive tour guide
More and more museums aim at enhancing their visitors' museum experiences in a personalized, intensive and engaging way inside the museum. The CHIP1 (Cultural Heritage Inform...
Ivo Roes, Natalia Stash, Yiwen Wang, Lora Aroyo