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» SEU tolerant device, circuit and processor design
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FPGA
2006
ACM
131views FPGA» more  FPGA 2006»
15 years 1 months ago
Yield enhancements of design-specific FPGAs
The high unit cost of FPGA devices often deters their use beyond the prototyping stage. Efforts have been made to reduce the part-cost of FPGA devices, resulting in the developmen...
Nicola Campregher, Peter Y. K. Cheung, George A. C...
FPGA
2009
ACM
159views FPGA» more  FPGA 2009»
15 years 4 months ago
Choose-your-own-adventure routing: lightweight load-time defect avoidance
Aggressive scaling increases the number of devices we can integrate per square millimeter but makes it increasingly difficult to guarantee that each device fabricated has the inte...
Raphael Rubin, André DeHon
DATE
2008
IEEE
182views Hardware» more  DATE 2008»
15 years 4 months ago
A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking
— As the feature size of transistors gets smaller, fabricating them becomes challenging. Manufacturing process follows various corrective design-for-manufacturing (DFM) steps to ...
Swaroop Ghosh, Patrick Ndai, Kaushik Roy
ISCA
2005
IEEE
119views Hardware» more  ISCA 2005»
15 years 3 months ago
Rescue: A Microarchitecture for Testability and Defect Tolerance
Scaling feature size improves processor performance but increases each device’s susceptibility to defects (i.e., hard errors). As a result, fabrication technology must improve s...
Ethan Schuchman, T. N. Vijaykumar
CODES
2010
IEEE
14 years 7 months ago
A task remapping technique for reliable multi-core embedded systems
With the continuous scaling of semiconductor technology, the life-time of circuit is decreasing so that processor failure becomes an important issue in MPSoC design. A software so...
Chanhee Lee, Hokeun Kim, Hae-woo Park, Sungchan Ki...