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» SEU tolerant device, circuit and processor design
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DAC
2006
ACM
15 years 10 months ago
FLAW: FPGA lifetime awareness
Aggressive scaling of technology has an adverse impact on the reliability of VLSI circuits. Apart from increasing transient error susceptibility, the circuits also become more vul...
Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie,...
MOBISYS
2008
ACM
15 years 9 months ago
Trustworthy and personalized computing on public kiosks
Many people desire ubiquitous access to their personal computing environments. We present a system in which a user leverages a personal mobile device to establish trust in a publi...
Scott Garriss, Ramón Cáceres, Stefan...
TVLSI
2008
150views more  TVLSI 2008»
14 years 9 months ago
Data Memory Subsystem Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance o...
M. Bennaser, Yao Guo, Csaba Andras Moritz
ISCA
2012
IEEE
320views Hardware» more  ISCA 2012»
13 years 4 days ago
Viper: Virtual pipelines for enhanced reliability
The reliability of future processors is threatened by decreasing transistor robustness. Current architectures focus on delivering high performance at low cost; lifetime device rel...
Andrea Pellegrini, Joseph L. Greathouse, Valeria B...
ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
13 years 4 days ago
Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures
A significant portion of the energy dissipated in modern integrated circuits is consumed by the overhead associated with timing guardbands that ensure reliable execution. Timing ...
Evgeni Krimer, Patrick Chiang, Mattan Erez