10 search results - page 1 / 2 » SWiTEST: A Switch Level Test Generation System for CMOS Comb... |
65
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DAC
1992
ACM
15 years 1 months ago
1992
ACM
CEC
2005
IEEE
15 years 3 months ago
2005
IEEE
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...
100
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ET
2010
14 years 7 months ago
2010
This work justifies several quantum gate level fault models and discusses the causal error mechanisms thwarting correct function. A quantum adaptation of the classical test set gen...
ICCAD
1997
IEEE
15 years 1 months ago
1997
IEEE
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...