314 search results - page 13 / 63 » Sanity Checks in Formal Verification |
115
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DAC
1996
ACM
15 years 3 months ago
1996
ACM
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
114
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FMCAD
1998
Springer
15 years 4 months ago
1998
Springer
We present a new approach to the verification of hardware systems with data dependencies using temporal logic symbolic model checking. As a benchmark we take Tomasulo's algori...
ASYNC
2007
IEEE
15 years 3 months ago
2007
IEEE
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architec...
100
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ENTCS
2006
14 years 11 months ago
2006
Patterns for property specification enable non-experts to write formal specifications that can be used for automatic model checking. The existing patterns identified in [6] allow ...
107
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FMCAD
2000
Springer
15 years 3 months ago
2000
Springer
Abstract. We present a formal verification methodology for datapathdominated hardware. This provides a systematic but flexible framework within which to organize the activities und...