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CODES
2003
IEEE
15 years 3 months ago
A low-cost memory architecture with NAND XIP for mobile embedded systems
NAND flash memory has become an indispensable component in mobile embedded systems because of its versatile features such as non-volatility, solid-state reliability, low cost and ...
Chanik Park, Jaeyu Seo, Sunghwan Bae, Hyojun Kim, ...
NOCS
2007
IEEE
15 years 4 months ago
On the Design of a Photonic Network-on-Chip
Recent remarkable advances in nanoscale siliconphotonic integrated circuitry specifically compatible with CMOS fabrication have generated new opportunities for leveraging the uni...
Assaf Shacham, Keren Bergman, Luca P. Carloni
VLSID
2003
IEEE
183views VLSI» more  VLSID 2003»
15 years 10 months ago
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks
We present an innovative design of an accurate, 2D DCT IDCT processor, which handles scaled and sub-sampled input blocks efficiently. In the IDCT mode, the latency of the processo...
Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van...
IPPS
2007
IEEE
15 years 4 months ago
A Landmark-based Index Architecture for General Similarity Search in Peer-to-Peer Networks
The indexing of complex data and similarity search plays an important role in many application areas. Traditional centralized index structure can not scale with the rapid prolifer...
Xiaoyu Yang, Yiming Hu
HOTI
2005
IEEE
15 years 3 months ago
Hybrid Cache Architecture for High Speed Packet Processing
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
Zhen Liu, Kai Zheng, Bin Liu