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ASPDAC
2008
ACM
97views Hardware» more  ASPDAC 2008»
15 years 2 months ago
A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures
Horizontally Partitioned Caches (HPCs) are a promising architectural feature to reduce the energy consumption of the memory subsystem. However, the energy reduction obtained using...
Aviral Shrivastava, Ilya Issenin, Nikil Dutt
164
Voted
SIGMOD
2009
ACM
122views Database» more  SIGMOD 2009»
16 years 23 days ago
Finding min-repros in database software
Testing and debugging database system applications is often challenging and time consuming. A database tester (or DB tester for short) has to detect a problem, determine why it ha...
Nicolas Bruno, Rimma V. Nehme
95
Voted
TCAD
2008
115views more  TCAD 2008»
15 years 14 days ago
Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories
Abstract--The fabrication of crossbar memories with sublithographic features is expected to be feasible within several emerging technologies; in all of them, the nanowire (NW) deco...
M. Haykel Ben Jamaa, Kirsten E. Moselund, David At...
145
Voted
HPCA
2011
IEEE
14 years 4 months ago
Archipelago: A polymorphic cache design for enabling robust near-threshold operation
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
99
Voted
DAC
1998
ACM
16 years 1 months ago
Code Compression for Embedded Systems
Memory is one of the most restricted resources in many modern embedded systems. Code compression can provide substantial savings in terms of size. In a compressed code CPU, a cach...
Haris Lekatsas, Wayne Wolf