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IPPS
2007
IEEE
15 years 8 months ago
A Study of Design Efficiency with a High-Level Language for FPGAs
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
Zain-ul-Abdin, Bertil Svensson
ISPA
2007
Springer
15 years 8 months ago
Parallelization Strategies for the Points of Interests Algorithm on the Cell Processor
The Cell processor is a typical example of a heterogeneous multiprocessor-on-chip architecture that uses several levels of parallelism to deliver high performance. Closing the gap ...
Tarik Saidani, Lionel Lacassagne, Samir Bouaziz, T...
CCGRID
2006
IEEE
15 years 8 months ago
ReCon: A Fast and Reliable Replica Retrieval Service for the Data Grid
The Data Grid provides a scalable infrastructure for storage resources and data distribution management. It also supports a variety of scientific applications that require access...
XiaoLi Zhou, Eunsung Kim, Jai Wug Kim, Heon Young ...
DATE
2009
IEEE
86views Hardware» more  DATE 2009»
15 years 9 months ago
A link arbitration scheme for quality of service in a latency-optimized network-on-chip
Abstract—Networks-on-chip (NoC) for general-purpose multiprocessors require quality of service mechanisms to allow realtime streaming applications to be executed along with laten...
Jonas Diemer, Rolf Ernst
SPAA
2012
ACM
13 years 4 months ago
Allowing each node to communicate only once in a distributed system: shared whiteboard models
In this paper we study distributed algorithms on massive graphs where links represent a particular relationship between nodes (for instance, nodes may represent phone numbers and ...
Florent Becker, Adrian Kosowski, Nicolas Nisse, Iv...