Sciweavers

399 search results - page 18 / 80
» Scalable Switching Testbed not
Sort
View
AIPS
1998
15 years 1 months ago
Flexible and Scalable Query Planning in Distributed and Heterogeneous Environments
We present the application of the Planning by Rewriting PbR framework to query planning in distributed and heterogeneous environments. PbR is a new paradigm for e cient high-quali...
José Luis Ambite, Craig A. Knoblock
ETS
2007
IEEE
109views Hardware» more  ETS 2007»
15 years 6 months ago
Test Configurations for Diagnosing Faulty Links in NoC Switches
The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. The method is based on functional fault models and it implements packet address dri...
Jaan Raik, Raimund Ubar, Vineeth Govind
HOTI
2002
IEEE
15 years 4 months ago
A Four-Terabit Single-Stage Packet Switch with Large Round-Trip Time Support
We present the architecture and practical VLSI implementation of a 4-Tb/s single-stage switch. It is based on a combined input- and crosspoint-queued structure with virtual output...
François Abel, Cyriel Minkenberg, Ronald P....
TON
2010
115views more  TON 2010»
14 years 6 months ago
Feedback-Based Scheduling for Load-Balanced Two-Stage Switches
Abstract--A framework for designing feedback-based scheduling algorithms is proposed for elegantly solving the notorious packet missequencing problem of a load-balanced switch. Unl...
Bing Hu, Kwan L. Yeung
DATE
2000
IEEE
132views Hardware» more  DATE 2000»
15 years 4 months ago
A Generic Architecture for On-Chip Packet-Switched Interconnections
This paper presents an architectural study of a scalable system-level interconnection template. We explain why the shared bus, which is today's dominant template, will not me...
Pierre Guerrier, Alain Greiner