Sciweavers

433 search results - page 28 / 87
» Scale in Chip Interconnect requires Network Technology
Sort
View
DATE
2002
IEEE
103views Hardware» more  DATE 2002»
15 years 2 months ago
Communication Mechanisms for Parallel DSP Systems on a Chip
We consider the implication of deep sub-micron VLSI technology on the design of communication frameworks for parallel DSP systems-on-chip. We assert that distributed data transfer...
Joseph Williams, Nevin Heintze, Bryan D. Ackland
68
Voted
DATE
2010
IEEE
192views Hardware» more  DATE 2010»
15 years 2 months ago
PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks
—Recent developments have shown the possibility of leveraging silicon nanophotonic technologies for chip-scale interconnection fabrics that deliver high bandwidth and power effi...
Johnnie Chan, Gilbert Hendry, Aleksandr Biberman, ...
IPPS
2007
IEEE
15 years 4 months ago
Optimizing the Fast Fourier Transform on a Multi-core Architecture
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
Long Chen, Ziang Hu, Junmin Lin, Guang R. Gao
80
Voted
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
15 years 1 months ago
Layout Driven Logic Restructuring/Decomposition
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
Massoud Pedram, Narasimha B. Bhat
FPGA
2003
ACM
137views FPGA» more  FPGA 2003»
15 years 2 months ago
Design of FPGA interconnect for multilevel metalization
How does multilevel metalization impact the design of FPGA interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the thirddi...
Raphael Rubin, André DeHon