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» Scale in Chip Interconnect requires Network Technology
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MTA
2000
108views more  MTA 2000»
14 years 9 months ago
Towards A New Authoring Methodology for Large-Scale Hypermedia Applications
As the amount of information technology increases, managing information resources, so that the correct people can find the information easily, becomes a critical issue. Hypermedia...
Ian Heath, Gary Wills, Richard Crowder, Wendy Hall...
TPDS
2008
134views more  TPDS 2008»
14 years 9 months ago
Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On th...
Ricardo Fernández Pascual, José M. G...
MICRO
2009
IEEE
124views Hardware» more  MICRO 2009»
15 years 4 months ago
ZerehCache: armoring cache architectures in high defect density technologies
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
ISCA
2008
IEEE
119views Hardware» more  ISCA 2008»
14 years 9 months ago
Technology-Driven, Highly-Scalable Dragonfly Topology
Evolving technology and increasing pin-bandwidth motivate the use of high-radix routers to reduce the diameter, latency, and cost of interconnection networks. High-radix networks,...
John Kim, William J. Dally, Steve Scott, Dennis Ab...
DFT
2008
IEEE
138views VLSI» more  DFT 2008»
15 years 4 months ago
Exploring Density-Reliability Tradeoffs on Nanoscale Substrates: When do smaller less reliable devices make sense?
It is widely recognized that device and interconnect fabrics at the nanoscale will be characterized by an increased susceptibility to transient faults. This appears to be intrinsi...
Andrey V. Zykov, Gustavo de Veciana