433 search results - page 58 / 87 » Scale in Chip Interconnect requires Network Technology |
120
click to vote
ANCS
2011
ACM
13 years 9 months ago
2011
ACM
The largest enterprise networks already contain hundreds of thousands of hosts. Enterprise networks are composed of Ethernet subnets interconnected by IP routers. These routers re...
90
Voted
BMCBI
2005
14 years 9 months ago
2005
Background: A major challenge in computational genomics is the development of methodologies that allow accurate genome-wide prediction of the regulatory targets of a transcription...
BMCBI
2007
14 years 9 months ago
2007
Background: Boolean network (BN) modeling is a commonly used method for constructing gene regulatory networks from time series microarray data. However, its major drawback is that...
DAC
2008
ACM
15 years 10 months ago
2008
ACM
Due to skewed scaling of interconnect delay and cell delay with technology scaling, modern VLSI timing closure requires use of extensive buffer insertion. Inserting a large number...
HPCA
1997
IEEE
15 years 1 months ago
1997
IEEE
Fast Ethernet and ATM are two attractive network technologies for interconnecting workstation clusters for parallel and distributed computing. This paper compares network interfac...