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» Scale in Chip Interconnect requires Network Technology
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CASES
2007
ACM
15 years 1 months ago
Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs
Advances in semiconductor technologies have placed MPSoCs center stage as a standard architecture for embedded applications of ever increasing complexity. Efficient utilization of...
Chengmo Yang, Alex Orailoglu
SIGMETRICS
2008
ACM
119views Hardware» more  SIGMETRICS 2008»
14 years 9 months ago
Network externalities and the deployment of security features and protocols in the internet
Getting new security features and protocols to be widely adopted and deployed in the Internet has been a continuing challenge. There are several reasons for this, in particular ec...
Marc Lelarge, Jean Bolot
JOIN
2007
96views more  JOIN 2007»
14 years 9 months ago
Universal Routing and Performance Assurance for Distributed Networks
In this paper, we show that universal routing can be achieved with low overhead in distributed networks. The validity of our results rests on a new network called the fat-stack. W...
Kevin F. Chen, Edwin Hsing-Mean Sha
TC
2011
14 years 4 months ago
Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines
—Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
MUE
2007
IEEE
120views Multimedia» more  MUE 2007»
15 years 4 months ago
Design and Implementation of Secure Communication Channels over UPnP Networks
The scale of smart living spaces can be varied from small, e.g. a household, to large, e.g. a building or a campus, scales. As the scale of the space increases, we can expect that...
Jiunn-Jye Lee, Chun-Ying Huang, Li-Yuan Lee, Chin-...