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» Scaling, Power and the Future of CMOS
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IEICET
2006
79views more  IEICET 2006»
14 years 9 months ago
System LSI: Challenges and Opportunities
End of CMOS scaling has been discussed in many places since the late 90's. Even if the end of CMOS scaling is irrelevant, it is for sure that we are facing a turning point in...
Tadahiro Kuroda
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
15 years 4 months ago
A low-SER efficient core processor architecture for future technologies
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
CASES
2008
ACM
14 years 11 months ago
StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems
Although CMOS feature size scaling has been the source of dramatic performance gains, it has lead to mounting reliability concerns due to increasing power densities and on-chip te...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason ...
IPPS
2007
IEEE
15 years 3 months ago
On the Path to Enable Multi-scale Biomolecular Simulations on PetaFLOPS Supercomputer with Multi-core Processors
1 Biological processes occurring inside cell involve multiple scales of time and length; many popular theoretical and computational multi-scale techniques utilize biomolecular simu...
Sadaf R. Alam, Pratul K. Agarwal
79
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ICALP
2009
Springer
15 years 4 months ago
Improved Bounds for Speed Scaling in Devices Obeying the Cube-Root Rule
Speed scaling is a power management technique that involves dynamically changing the speed of a processor. This gives rise to dualobjective scheduling problems, where the operating...
Nikhil Bansal, Ho-Leung Chan, Kirk Pruhs, Dmitriy ...