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» Scaling, Power and the Future of CMOS
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GLVLSI
2007
IEEE
172views VLSI» more  GLVLSI 2007»
15 years 4 months ago
The effect of temperature on cache size tuning for low energy embedded systems
Energy consumption is a major concern in embedded computing systems. Several studies have shown that cache memories account for about 40% or more of the total energy consumed in t...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...
TVLSI
2008
197views more  TVLSI 2008»
14 years 9 months ago
Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology
-- Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing the subthreshold a...
Behnam Amelifard, Farzan Fallah, Massoud Pedram
ICALT
2003
IEEE
15 years 2 months ago
Visualization of the Learning Process Using Concept Mapping
Visualization of the learning processes is a powerful way to help students to understand their curricula and the structure behind them. CME2 is a prototype software of this favour...
Jussi A. Nuutinen, Erkki Sutinen
ASPLOS
2004
ACM
15 years 3 months ago
Heat-and-run: leveraging SMT and CMP to manage power density through the operating system
Power density in high-performance processors continues to increase with technology generations as scaling of current, clock speed, and device density outpaces the downscaling of s...
Mohamed A. Gomaa, Michael D. Powell, T. N. Vijayku...
ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
15 years 2 months ago
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
Anoop Iyer, Diana Marculescu