35 search results - page 5 / 7 » Scan Test Planning for Power Reduction |
153
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VTS
2006
IEEE
15 years 7 months ago
2006
IEEE
— In this paper, an algorithm for scan vector ordering, PEAKASO, is proposed to minimize the peak temperature during scan testing. Given a circuit with scan and the scan vectors,...
124
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DATE
2010
IEEE
15 years 4 months ago
2010
IEEE
Various X-filling methods have been proposed for reducing the shift and/or capture power in scan testing. The main drawback of these methods is that X-filling for low power leads t...
139
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DFT
2002
IEEE
15 years 6 months ago
2002
IEEE
Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthe...
105
Voted
ICCD
2004
IEEE
15 years 10 months ago
2004
IEEE
— Reduction in test power is important to improve battery life in portable devices employing periodic self-test, to increase reliability of testing and to reduce test-cost. In sc...
110
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ICCAD
2008
IEEE
15 years 10 months ago
2008
IEEE
Large test data volume and high test power are two of the major concerns for the industry when testing large integrated circuits. With given test cubes in scan-based testing, the ...