469 search results - page 7 / 94 » Scheduler Modeling Based on the Controller Synthesis Paradig... |
RTCSA
1999
IEEE
15 years 1 months ago
1999
IEEE
Abstract. We present an approach to static priority preemptive process scheduling for the synthesis of hard realtime distributed embedded systems where communication plays an impor...
GLVLSI
2007
IEEE
15 years 1 months ago
2007
IEEE
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
An inherent performance gap between custom designs and ASICs is one of the reasons why many designers still start their designs from register transfer level (RTL) description rath...
ICCD
2002
IEEE
2002
IEEE
Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors
15 years 6 months ago
A circuit or circuit component that does not contain any spurious switching activity, i.e., activity that is not required by its specified functionality, is called perfectly power...
DATE
1999
IEEE
15 years 1 months ago
1999
IEEE
We introduce a novel behavioral test synthesis methodology that attempts to increase module reachability, driven by powerful global design path analysis. Based on the notion of tr...