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IPPS
2006
IEEE
15 years 3 months ago
FIFO scheduling of divisible loads with return messages under the one-port model
This paper deals with scheduling divisible load applications on star networks, in presence of return messages. This work is a follow-on of [6, 7], where the same problem was consi...
Olivier Beaumont, Loris Marchal, Veronika Rehn, Yv...
DATE
2009
IEEE
149views Hardware» more  DATE 2009»
15 years 4 months ago
An ILP formulation for task mapping and scheduling on multi-core architectures
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...
Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tugh...
ISCAPDCS
2001
14 years 11 months ago
Performance Evaluation of a Non-Blocking Multithreaded Architecture for Embedded, Real-Time and DSP Applications
This paper presents the evaluation of a non-blocking, decoupled memory/execution, multithreaded architecture known as the Scheduled Dataflow (SDF). The major recent trend in digit...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
CASES
2006
ACM
15 years 3 months ago
Integrated scratchpad memory optimization and task scheduling for MPSoC architectures
Multiprocessor system-on-chip (MPSoC) is an integrated circuit containing multiple instruction-set processors on a single chip that implements most of the functionality of a compl...
Vivy Suhendra, Chandrashekar Raghavan, Tulika Mitr...
71
Voted
DATE
2005
IEEE
110views Hardware» more  DATE 2005»
15 years 3 months ago
Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration
attributed to the high regularity of memories, PAs and FPGAs, and the ease with which they can be tested and reconfigured to avoid faulty elements. Digital microfluidicsbased bioch...
Fei Su, Krishnendu Chakrabarty, Vamsee K. Pamula