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SAC
2009
ACM
14 years 4 months ago
Celling SHIM: compiling deterministic concurrency to a heterogeneous multicore
Parallel architectures are the way of the future, but are notoriously difficult to program. In addition to the low-level constructs they often present (e.g., locks, DMA, and non-...
Nalini Vasudevan, Stephen A. Edwards
DATE
2010
IEEE
124views Hardware» more  DATE 2010»
14 years 2 months ago
Reuse-aware modulo scheduling for stream processors
—This paper presents reuse-aware modulo scheduling to maximizing stream reuse and improving concurrency for stream-level loops running on stream processors. The novelty lies in t...
Li Wang, Jingling Xue, Xuejun Yang
ISPA
2007
Springer
14 years 3 months ago
Parallelization Strategies for the Points of Interests Algorithm on the Cell Processor
The Cell processor is a typical example of a heterogeneous multiprocessor-on-chip architecture that uses several levels of parallelism to deliver high performance. Closing the gap ...
Tarik Saidani, Lionel Lacassagne, Samir Bouaziz, T...
CF
2005
ACM
13 years 11 months ago
An efficient wakeup design for energy reduction in high-performance superscalar processors
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
Kuo-Su Hsiao, Chung-Ho Chen
IPPS
2007
IEEE
14 years 3 months ago
RAxML-Cell: Parallel Phylogenetic Tree Inference on the Cell Broadband Engine
Computational phylogeny is a challenging application even for the most powerful supercomputers. It is also an ideal candidate for benchmarking emerging multiprocessor architecture...
Filip Blagojevic, Alexandros Stamatakis, Christos ...