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ISSS
1995
IEEE
161views Hardware» more  ISSS 1995»
15 years 1 months ago
Synthesis of pipelined DSP accelerators with dynamic scheduling
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
Patrick Schaumont, Bart Vanthournout, Ivo Bolsens,...
SIGARCH
2008
107views more  SIGARCH 2008»
14 years 9 months ago
A lightweight streaming layer for multicore execution
As multicore architectures gain widespread use, it becomes increasingly important to be able to harness their additional processing power to achieve higher performance. However, e...
David Zhang, Qiuyuan J. Li, Rodric Rabbah, Saman A...
IPPS
2007
IEEE
15 years 3 months ago
Porting the GROMACS Molecular Dynamics Code to the Cell Processor
The Cell processor offers substantial computational power which can be effectively utilized only if application design and implementation are tuned to the Cell architecture. In th...
Stephen Olivier, Jan Prins, Jeff Derby, Ken V. Vu
EGH
2009
Springer
14 years 7 months ago
Stream compaction for deferred shading
The GPU leverages SIMD efficiency when shading because it rasterizes a triangle at a time, running the same shader on all of its fragments. Ray tracing sacrifices this shader cohe...
Jared Hoberock, Victor Lu, Yuntao Jia, John C. Har...
CP
2008
Springer
14 years 11 months ago
A Constraint Programming Approach for Allocation and Scheduling on the CELL Broadband Engine
The Cell BE processor provides both scalable computation power and flexibility, and it is already being adopted for many computational intensive applications like aerospace, defens...
Luca Benini, Michele Lombardi, Michela Milano, Mar...