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» Scheduling for Reduced CPU Energy
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130
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ASPDAC
2005
ACM
104views Hardware» more  ASPDAC 2005»
15 years 3 months ago
On multiple-voltage high-level synthesis using algorithmic transformations
— This paper presents a multiple-voltage high-level synthesis methodology for low power DSP applications using algorithmic transformation techniques. Our approach is motivated by...
Hsueh-Chih Yang, Lan-Rong Dung
ISCA
2012
IEEE
234views Hardware» more  ISCA 2012»
13 years 4 months ago
PARDIS: A programmable memory controller for the DDRx interfacing standards
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
Mahdi Nazm Bojnordi, Engin Ipek
136
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MM
2003
ACM
161views Multimedia» more  MM 2003»
15 years 7 months ago
Integrated power management for video streaming to mobile handheld devices
Optimizing user experience for streaming video applications on handheld devices is a significant research challenge. In this paper, we propose an integrated power management appr...
Shivajit Mohapatra, Radu Cornea, Nikil D. Dutt, Al...
120
Voted
IJNSEC
2010
163views more  IJNSEC 2010»
14 years 8 months ago
Evaluating the Effects of Symmetric Cryptography Algorithms on Power Consumption for Different Data Types
As the importance and the value of exchanged data over the Internet or other media types are increasing, the search for the best solution to offer the necessary protection against...
Diaa Salama Abdul Minaam, Hatem M. Abdual-Kader, M...
127
Voted
ICCAD
2009
IEEE
179views Hardware» more  ICCAD 2009»
14 years 11 months ago
Automatic memory partitioning and scheduling for throughput and power optimization
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
Jason Cong, Wei Jiang, Bin Liu, Yi Zou