221 search results - page 12 / 45 » Scheduling instruction effects for a statically pipelined pr... |
IPPS
2006
IEEE
15 years 4 months ago
2006
IEEE
The performance requirements for contemporary microprocessors are increasing as rapidly as their number of applications grows. By accelerating the clock, performance can be gained...
CSSE
2008
IEEE
15 years 4 months ago
2008
IEEE
Instruction-Set Simulators (ISS) are indispensable tools for studying new architectures. There are several alternatives to achieve instruction set simulation, such as interpretive...
CGO
2004
IEEE
15 years 2 months ago
2004
IEEE
Application-specific instruction set processors (ASIPs) have the potential to meet the challenging cost, performance, and power goals of future embedded processors by customizing ...
PLDI
1995
ACM
15 years 1 months ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
IPPS
2006
IEEE
15 years 4 months ago
2006
IEEE
The industry is rapidly moving towards the adoption of Chip Multi-Processors (CMPs) of Simultaneous MultiThreaded (SMT) cores for general purpose systems. The most prominent use o...