221 search results - page 22 / 45 » Scheduling instruction effects for a statically pipelined pr... |
ICS
2005
Tsinghua U.
15 years 4 months ago
2005
Tsinghua U.
With the increasing performance gap between the processor and the memory, the importance of caches is increasing for high performance processors. However, with reducing feature si...
IEEEPACT
2003
IEEE
15 years 3 months ago
2003
IEEE
Simultaneous multithreading (SMT) increases processor throughput by multiplexing resources among several threads. Despite the commercial availability of SMT processors, several as...
ISCA
2003
IEEE
15 years 3 months ago
2003
IEEE
Scaling of CMOS technology causes the power supply voltages to fall and supply currents to rise at the same time as operating speeds are increasing. Falling supply voltages cause ...
GLVLSI
2008
IEEE
15 years 4 months ago
2008
IEEE
Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which...
HPCA
2004
IEEE
15 years 10 months ago
2004
IEEE
Branch misprediction penalty consists of two components: the time wasted on mis-speculative execution until the mispredicted branch is resolved and the time to restart the pipelin...