221 search results - page 25 / 45 » Scheduling instruction effects for a statically pipelined pr... |
HCW
2000
IEEE
15 years 2 months ago
2000
IEEE
Recently, we presented two very low-cost approaches to compile-time list scheduling where the tasks’ priorities are computed statically or dynamically, respectively. For homogen...
ICCD
2005
IEEE
15 years 4 months ago
2005
IEEE
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
ICS
2004
Tsinghua U.
15 years 3 months ago
2004
Tsinghua U.
In contemporary out-of-order superscalar design, high IPC is mainly achieved by exposing high instruction level parallelism (ILP). Scaling issue window size can certainly provide ...
71
Voted
IPPS
2007
IEEE
15 years 4 months ago
2007
IEEE
Parallel processing using multiple processors is a well-established technique to accelerate many different classes of applications. However, as the density of chips increases, ano...
RTSS
2003
IEEE
15 years 3 months ago
2003
IEEE
This paper presents a quantification of the timing effects that advanced processor features like data and instruction cache, pipelines, branch prediction units and out-oforder ex...