221 search results - page 30 / 45 » Scheduling instruction effects for a statically pipelined pr... |
PLDI
2005
ACM
15 years 4 months ago
2005
ACM
Software pipelining of a multi-dimensional loop is an important optimization that overlaps the execution of successive outermost loop iterations to explore instruction-level paral...
HPCA
2003
IEEE
15 years 10 months ago
2003
IEEE
To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in applications. A fundament...
CGO
2004
IEEE
15 years 2 months ago
2004
IEEE
Traditionally, software pipelining is applied either to the innermost loop of a given loop nest or from the innermost loop to the outer loops. In a companion paper, we proposed a ...
SBACPAD
2008
IEEE
15 years 4 months ago
2008
IEEE
The performance impact of the Physical Register File (PRF) size on Simultaneous Multithreading processors has not been extensively studied in spite of being a critical shared reso...
CASES
2007
ACM
15 years 2 months ago
2007
ACM
This paper tackles the problem of providing correct information about program variable values in a software-pipelined loop through a non-transparent debugging approach. Since mode...