221 search results - page 8 / 45 » Scheduling instruction effects for a statically pipelined pr... |
IEEEPACT
2003
IEEE
15 years 3 months ago
2003
IEEE
Effective modeling and management of hardware resources have always been critical toward generating highly efficient code in static compilers. With Just-In-Time compilation and dy...
IEEEPACT
2002
IEEE
15 years 3 months ago
2002
IEEE
Traditional compilers perform their code generation tasks based on a fixed, pre-determined instruction set. This paper describes the implementation of a compiler that determines ...
103
Voted
DAC
1996
ACM
15 years 2 months ago
1996
ACM
Abstract -- This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (Application Specific Integrated Pro...
IPPS
2005
IEEE
15 years 4 months ago
2005
IEEE
An architecture for a reconfigurable superscalar processor is described in which some of its execution units are implemented in reconfigurable hardware. The overall configuration ...
CC
2000
Springer
14 years 10 months ago
2000
Springer
The performance of a Java Virtual Machine (JVM) interpreter running on a very long instruction word (VLIW) processor can be improved by means of pipelining. While one bytecode is i...