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2006
IEEE
15 years 6 months ago
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
Martijn Coenen, Srinivasan Murali, Andrei Radulesc...
DATE
2006
IEEE
84views Hardware» more  DATE 2006»
15 years 6 months ago
Vulnerability analysis of L2 cache elements to single event upsets
Memory elements are the most vulnerable system component to soft errors. Since memory elements in cache arrays consume a large fraction of the die in modern microprocessors, the p...
Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Ta...
DFT
2006
IEEE
105views VLSI» more  DFT 2006»
15 years 6 months ago
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
1 High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range,...
Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinge...
127
Voted
FCCM
2006
IEEE
195views VLSI» more  FCCM 2006»
15 years 6 months ago
A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2)
This paper presents a hardware-optimized variant of the well-known Gaussian elimination over GF(2) and its highly efficient implementation. The proposed hardware architecture, we...
Andrey Bogdanov, M. C. Mertens
90
Voted
GMP
2006
IEEE
15 years 6 months ago
Subdivision Termination Criteria in Subdivision Multivariate Solvers
Abstract. The need for robust solutions for sets of non-linear multivariate constraints or equations needs no motivation. Subdivision-based multivariate constraint solvers [1–3] ...
Iddo Hanniel, Gershon Elber
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