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83
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DFT
2005
IEEE
83views VLSI» more  DFT 2005»
15 years 3 months ago
An ILP Formulation for Yield-driven Architectural Synthesis
Data flow graph dominant designs, such as communication video and audio applications, are common in today’s IC industry. In these designs, the datapath resources (e.g., adders,...
Zhaojun Wo, Israel Koren, Maciej J. Ciesielski
ASPDAC
2005
ACM
134views Hardware» more  ASPDAC 2005»
15 years 3 months ago
Wire congestion and thermal aware 3D global placement
— The recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wirelength. However, wire congestion and thermal issues are exacerbated d...
Karthik Balakrishnan, Vidit Nanda, Siddharth Easwa...
CF
2004
ACM
15 years 2 months ago
Designing and testing fault-tolerant techniques for SRAM-based FPGAs
This paper discusses fault-tolerant techniques for SRAM-based FPGAs. These techniques can be based on circuit level modifications, with obvious modifications in the programmable a...
Fernanda Lima Kastensmidt, Gustavo Neuberger, Luig...
SMA
2003
ACM
118views Solid Modeling» more  SMA 2003»
15 years 2 months ago
Graph based topological analysis of tessellated surfaces
In this paper a graph-based method is presented which not only characterizes topological classification of the tessellated surfaces but also simultaneously generates the substanti...
Tula Ram Ban, Dibakar Sen
80
Voted
SIGECOM
2010
ACM
184views ECommerce» more  SIGECOM 2010»
15 years 2 months ago
Computing pure strategy nash equilibria in compact symmetric games
We analyze the complexity of computing pure strategy Nash equilibria (PSNE) in symmetric games with a fixed number of actions. We restrict ourselves to “compact” representati...
Christopher Thomas Ryan, Albert Xin Jiang, Kevin L...