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FCCM
2006
IEEE
113views VLSI» more  FCCM 2006»
15 years 10 months ago
GraphStep: A System Architecture for Sparse-Graph Algorithms
— Many important applications are organized around long-lived, irregular sparse graphs (e.g., data and knowledge bases, CAD optimization, numerical problems, simulations). The gr...
Michael DeLorimier, Nachiket Kapre, Nikil Mehta, D...
ASPLOS
2006
ACM
15 years 10 months ago
Software-based instruction caching for embedded processors
While hardware instruction caches are present in virtually all general-purpose and high-performance microprocessors today, many embedded processors use SRAM or scratchpad memories...
Jason E. Miller, Anant Agarwal
STOC
2006
ACM
121views Algorithms» more  STOC 2006»
15 years 10 months ago
On adequate performance measures for paging
Memory management is a fundamental problem in computer architecture and operating systems. We consider a two-level memory system with fast, but small cache and slow, but large mai...
Konstantinos Panagiotou, Alexander Souza
ISCA
2005
IEEE
144views Hardware» more  ISCA 2005»
15 years 10 months ago
Scalable Load and Store Processing in Latency Tolerant Processors
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth...
SI3D
2005
ACM
15 years 10 months ago
Texture sprites: texture elements splatted on surfaces
We present a new interactive method to texture complex geometries at very high resolution, while using little memory and without the need for a global planar parameterization. We ...
Sylvain Lefebvre, Samuel Hornus, Fabrice Neyret
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