Sciweavers

7 search results - page 1 / 2
» Sensitivity Based Link Insertion for Variation Tolerant Cloc...
Sort
View
ISQED
2007
IEEE
127views Hardware» more  ISQED 2007»
15 years 3 months ago
Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Ch...
ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
15 years 6 months ago
Statistical based link insertion for robust clock network design
We present a statistical based non-tree clock distribution construction algorithm that starts with a tree and incrementally insert cross links, such that the skew variation of the...
Wai-Ching Douglas Lam, J. Jam, Cheng-Kok Koh, Venk...
52
Voted
ISPD
2006
ACM
91views Hardware» more  ISPD 2006»
15 years 3 months ago
Variation tolerant buffered clock network synthesis with cross links
Anand Rajaram, David Z. Pan
DAC
2004
ACM
15 years 10 months ago
Reducing clock skew variability via cross links
Increasingly significant variational effects present a great challenge for delivering desired clock skew reliably. Non-tree clock network has been recognized as a promising approac...
Anand Rajaram, Jiang Hu, Rabi N. Mahapatra
79
Voted
TVLSI
2010
14 years 4 months ago
Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
Rupak Samanta, Jiang Hu, Peng Li