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CDC
2009
IEEE
115views Control Systems» more  CDC 2009»
14 years 11 months ago
A multiplay model for rate-independent and rate-dependent hysteresis with nonlocal memory
Abstract-- We consider the multiplay model for hysteresis with nonlocal memory. This model consists of N mass/spring/dashpot with deadzone elements. The hysteresis map of the multi...
Bojana Drincic, Dennis S. Bernstein
HICSS
1994
IEEE
152views Biometrics» more  HICSS 1994»
15 years 5 months ago
Simple COMA Node Implementations
Shared memory architectures often have caches to reduce the number of slow remote memory accesses. The largest possible caches exist in shared memory architectures called Cache-On...
Erik Hagersten, Ashley Saulsbury, Anders Landin
POPL
1999
ACM
15 years 6 months ago
Typed Memory Management in a Calculus of Capabilities
An increasing number of systems rely on programming language technology to ensure safety and security of low-level code. Unfortunately, these systems typically rely on a complex, ...
Karl Crary, David Walker, J. Gregory Morrisett
IPPS
2006
IEEE
15 years 7 months ago
Helper thread prefetching for loosely-coupled multiprocessor systems
This paper presents a helper thread prefetching scheme that is designed to work on loosely-coupled processors, such as in a standard chip multi-processor (CMP) system and in an in...
Changhee Jung, Daeseob Lim, Jaejin Lee, Yan Solihi...
ISCA
2006
IEEE
125views Hardware» more  ISCA 2006»
15 years 7 months ago
Architectural Semantics for Practical Transactional Memory
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
Austen McDonald, JaeWoong Chung, Brian D. Carlstro...