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76
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MICRO
2006
IEEE
79views Hardware» more  MICRO 2006»
15 years 3 months ago
Fair Queuing Memory Systems
We propose and evaluate a multi-thread memory scheduler that targets high performance CMPs. The proposed memory scheduler is based on concepts originally developed for network fai...
Kyle J. Nesbit, Nidhi Aggarwal, James Laudon, Jame...
74
Voted
DATE
2007
IEEE
105views Hardware» more  DATE 2007»
15 years 4 months ago
Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison
We propose in this paper an algorithm for off-line selection of the contents of on-chip memories. The algorithm supports two types of on-chip memories, namely locked caches and sc...
Isabelle Puaut, Christophe Pais
FPGA
2011
ACM
330views FPGA» more  FPGA 2011»
14 years 1 months ago
CoRAM: an in-fabric memory architecture for FPGA-based computing
FPGAs have been used in many applications to achieve orders-of-magnitude improvement in absolute performance and energy efficiency relative to conventional microprocessors. Despit...
Eric S. Chung, James C. Hoe, Ken Mai
ICDCN
2012
Springer
13 years 5 months ago
Lifting the Barriers - Reducing Latencies with Transparent Transactional Memory
Synchronization in distributed systems is expensive because, in general, threads must stall to obtain a lock or to operate on volatile data. Transactional memory, on the other hand...
Annette Bieniusa, Thomas Fuhrmann
NN
2011
Springer
217views Neural Networks» more  NN 2011»
14 years 14 days ago
A neurodynamical model for working memory
Neurodynamical models of working memory (WM) should provide mechanisms for storing, maintaining, retrieving, and deleting information. Many models address only a subset of these a...
Razvan Pascanu, Herbert Jaeger