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HPCA
2002
IEEE
16 years 4 months ago
The Minimax Cache: An Energy-Efficient Framework for Media Processors
This work is based on our philosophy of providing interlayer system-level power awareness in computing systems [26, 27]. Here, we couple this approach with our vision of multipart...
Osman S. Unsal, Israel Koren, C. Mani Krishna, Csa...
HPCA
2001
IEEE
16 years 4 months ago
Automatically Mapping Code on an Intelligent Memory Architecture
This paper presents an algorithm to automatically map code on a generic intelligent memory system that consists of a host processor and a simpler memory processor. To achieve high...
Jaejin Lee, Yan Solihin, Josep Torrellas
PPOPP
2010
ACM
16 years 1 months ago
Modeling transactional memory workload performance
Transactional memory promises to make parallel programming easier than with fine-grained locking, while performing just as well. This performance claim is not always borne out bec...
Donald E. Porter, Emmett Witchel
DATE
2009
IEEE
117views Hardware» more  DATE 2009»
15 years 11 months ago
Using dynamic compilation for continuing execution under reduced memory availability
—This paper explores the use of dynamic compilation for continuing execution even if one or more of the memory banks used by an application become temporarily unavailable (but th...
Ozcan Ozturk, Mahmut T. Kandemir
ISPASS
2005
IEEE
15 years 10 months ago
Accelerating Multiprocessor Simulation with a Memory Timestamp Record
We introduce a fast and accurate technique for initializing the directory and cache state of a multiprocessor system based on a novel software structure called the memory timestam...
Kenneth C. Barr, Heidi Pan, Michael Zhang, Krste A...